1. Field of the Invention
The present invention is directed to a semiconductor memory cell having a grooved planar transfer device, and methods for making thereof, and more particularly, to a DRAM (dynamic random access memory) cell having an increased channel length resulting from the groove.
2. Discussion of the Prior Art
There is much interest to scale down densely packed semiconductor devices on an integrated circuit (IC) chip to reduce the size and power consumption of the chip, and allow faster operation. In order to achieve the high packing density necessary for Gbit memory applications, such as 1 Gbit and beyond, it is crucial to shrink the size of an individual memory cell as much as possible.
FIG. 1 shows a schematic of a typical DRAM cell 100 having a field effect transistor (FET) 105 and a storage capacitor C.sub.s The gate of the FET 105 acts as the wordline W/L. A bitline B/L is connected to one terminal of the FET 105, which terminal is the source or drain of the DRAM, depending on the application, such as read and write operations. The other DRAM terminal is connected to a strap or storage node 110 of the storage capacitor C.sub.s. The other terminal of the storage capacitor C.sub.s is referred to as a plate 115. When the FET 105 is turned on by an appropriate signal on the wordline W/L, data is transferred between the bitline B/L and the storage node 110.
In conventional designs that use planar transistors, the cell size is minimized by scaling lithographic features F. F is the minimum linewidth of the feature size that can be patterned with lithography. Accordingly, if a minimum cell size is to be obtained, it is necessary to reduce the size of the transistor 105 of FIG. 1 as much as possible. This reduces the gate channel length. However, shorter gate channel lengths increase leakage currents between the storage node 110 and bitline B/L to unacceptable levels. The reduced gate channel lengths degrade subthreshold leakage, and hence the retention time. Subthreshold leakage may be reduced by increasing the channel doping concentration. However, this increases and degrades junction leakage, which also reduces retention time.
In light of the foregoing, there is a need for a high density memory cell having a proper gate channel length, without increasing the lateral area of the cell or without increasing the doping concentration in the channel of the FET array.